VISCUBE: A multi-layer vision chip

Ákos Zarándy, Csaba Rekeczky, Péter Földesy, Ricardo Carmona-Galán, Gustavo Liñán Cembrano, Soós Gergely, Ángel Rodríguez-Vázquez, Tamás Roska

Research output: Chapter

1 Citation (Scopus)

Abstract

Vertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital processor arrays on a four layer structure is introduced. The mixed-signal processor array is designed to perform early image processing, while the role of the digital processor array is to accomplish foveal processing. The architecture supports multiscale, multifovea processing. The chip has been designed on a 0.15um feature sized 3DM2 SOI technology provided by MIT Lincoln Laboratory.

Original languageEnglish
Title of host publicationFocal-Plane Sensor-Processor Chips
PublisherSpringer New York
Pages181-208
Number of pages28
ISBN (Print)9781441964748
DOIs
Publication statusPublished - dec. 1 2011

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Zarándy, Á., Rekeczky, C., Földesy, P., Carmona-Galán, R., Cembrano, G. L., Gergely, S., Rodríguez-Vázquez, Á., & Roska, T. (2011). VISCUBE: A multi-layer vision chip. In Focal-Plane Sensor-Processor Chips (pp. 181-208). Springer New York. https://doi.org/10.1007/978-1-4419-6475-5_8