Electro-thermal simulation for the prediction of chip operation within the package

M. Rencz, V. Székely, A. Poppe, K. Torki, B. Courtois

Research output: Conference article

17 Citations (Scopus)


The device level electro-thermal simulation of analog circuits and the logical gate level logi-thermal simulation of digital circuits are addressed in the paper. After presenting the main algorithms realization questions are also discussed. For both the electro-thermal cases simulated results of realized structures are presented. These are compared with benchmark results, proving the applicability and the accuracy of the methods.

Original languageEnglish
Pages (from-to)168-175
Number of pages8
JournalAnnual IEEE Semiconductor Thermal Measurement and Management Symposium
Publication statusPublished - jan. 1 2003
EventNineteents Annual IEEE Semiconductor Thermal Measurement And Management Symposium - San Jose, CA, United States
Duration: márc. 11 2003márc. 13 2003

ASJC Scopus subject areas

  • Instrumentation
  • Electrical and Electronic Engineering

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