3D integrated scalable focal-plane processor array

Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska

Research output: Conference contribution

3 Citations (Scopus)

Abstract

The ASIC implementation of a 64×64 sized mixedsignal Cellular Visual Microprocessor architecture with digital processors is described. Measurement results are shown. The architecture is composed of a regular photosensor readout circuit array, prepared for 3D sensor integration, an array of identical SIMD processing elements, and central program scheduler. The processing architecture supports cluster formation of differently parameterized arrays.

Original languageEnglish
Title of host publicationEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
PublisherIEEE Computer Society
Pages954-957
Number of pages4
ISBN (Print)1424413427, 9781424413423
DOIs
Publication statusPublished - jan. 1 2007
EventEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain
Duration: aug. 26 2007aug. 30 2007

Publication series

NameEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007

Other

OtherEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
CountrySpain
CitySeville
Period8/26/078/30/07

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

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    Földesy, P., Zarándy, Á., Rekeczky, C., & Roska, T. (2007). 3D integrated scalable focal-plane processor array. In European Conference on Circuit Theory and Design 2007, ECCTD 2007 (pp. 954-957). [4529756] (European Conference on Circuit Theory and Design 2007, ECCTD 2007). IEEE Computer Society. https://doi.org/10.1109/ECCTD.2007.4529756