A novel ramped RTA technique is proposed for efficient low thermal budget post-implantation annealing of low-dose high energy P-implanted silicon wafers. Results obtained with this short effective annealing time of 300ms on 3inches substrates proved quite convincing in comparison with conventional furnace anneal performance. Full activation, minimum profile motion and generation rates below 0.3mA/cm3 could be achieved in the subsurface region, which is of interest for device applications. Inhomogeneity of the sheet resistivity due to transient temperature gradients across the wafer remained at 2%, comparable to or lower than in furnace annealed samples.
|Number of pages||4|
|Publication status||Published - Dec 1 1990|
|Event||22nd International Conference on Solid State Devices and Materials - Sendai, Jpn|
Duration: Aug 22 1990 → Aug 24 1990
|Other||22nd International Conference on Solid State Devices and Materials|
|Period||8/22/90 → 8/24/90|
ASJC Scopus subject areas