Towards design and validation of mixed-technology SOCs

S. Mir, B. Charlot, G. Nicolescu, P. Coste, F. Parrain, N. Zergainoh, B. Courtois, A. Jerraya, M. Rencz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS+micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on fingerprint recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multi-language/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages29-33
Number of pages5
Publication statusPublished - 2000
EventGLSVLSI 2000: 10th Great Lakes Symposium on VLSI - Chicago, IL, USA
Duration: Mar 2 2000Mar 4 2000

Other

OtherGLSVLSI 2000: 10th Great Lakes Symposium on VLSI
CityChicago, IL, USA
Period3/2/003/4/00

Fingerprint

MEMS
Sensors
Specifications
Hardware
Micromachining
Testing
Hybrid systems
Packaging
Engines
Costs
Hot Temperature
Intellectual property core

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mir, S., Charlot, B., Nicolescu, G., Coste, P., Parrain, F., Zergainoh, N., ... Rencz, M. (2000). Towards design and validation of mixed-technology SOCs. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 29-33). IEEE.

Towards design and validation of mixed-technology SOCs. / Mir, S.; Charlot, B.; Nicolescu, G.; Coste, P.; Parrain, F.; Zergainoh, N.; Courtois, B.; Jerraya, A.; Rencz, M.

Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, 2000. p. 29-33.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mir, S, Charlot, B, Nicolescu, G, Coste, P, Parrain, F, Zergainoh, N, Courtois, B, Jerraya, A & Rencz, M 2000, Towards design and validation of mixed-technology SOCs. in Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, pp. 29-33, GLSVLSI 2000: 10th Great Lakes Symposium on VLSI, Chicago, IL, USA, 3/2/00.
Mir S, Charlot B, Nicolescu G, Coste P, Parrain F, Zergainoh N et al. Towards design and validation of mixed-technology SOCs. In Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE. 2000. p. 29-33
Mir, S. ; Charlot, B. ; Nicolescu, G. ; Coste, P. ; Parrain, F. ; Zergainoh, N. ; Courtois, B. ; Jerraya, A. ; Rencz, M. / Towards design and validation of mixed-technology SOCs. Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, 2000. pp. 29-33
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