Studying the influence of chip temperatures on timing integrity using improved power modeling

András Timár, Márta Rencz

Research output: Contribution to journalArticle


Thermal side-effects can detrimentally influence operation of integrated circuits. The increase of temperature changes the devices' characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also briefly presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperaturedependent delays during the running simulation. Also various aspects of power characterization methods are also presented which were used throughout the experiments.

Original languageEnglish
Pages (from-to)531-540
Number of pages10
JournalJournal of Low Power Electronics
Issue number4
Publication statusPublished - Dec 1 2011


  • Delay Back-Annotation
  • Electro-Thermal Simulation
  • Temperature Distribution
  • Timing Integrity

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Studying the influence of chip temperatures on timing integrity using improved power modeling'. Together they form a unique fingerprint.

  • Cite this