Thermal (side-)effects can detrimentally influence operation of integrated circuits. The increase of temperature changes the devices' characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology as well as a tool to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also briefly presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperature-dependent delays during the running simulation.