Studying the influence of chip temperatures on timing integrity

András Timár, Márta Rencz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Thermal (side-)effects can detrimentally influence operation of integrated circuits. The increase of temperature changes the devices' characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology as well as a tool to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also briefly presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperature-dependent delays during the running simulation.

Original languageEnglish
Title of host publicationLATW 2011 - 12th IEEE Latin-American Test Workshop
DOIs
Publication statusPublished - Sep 15 2011
Event12th IEEE Latin-American Test Workshop, LATW 2011 - Porto de Galinhas, Brazil
Duration: Mar 27 2011Mar 30 2011

Publication series

NameLATW 2011 - 12th IEEE Latin-American Test Workshop

Other

Other12th IEEE Latin-American Test Workshop, LATW 2011
CountryBrazil
CityPorto de Galinhas
Period3/27/113/30/11

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Keywords

  • delay back-annotation
  • electro-thermal simulation
  • temperature distribution
  • timing integrity

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Timár, A., & Rencz, M. (2011). Studying the influence of chip temperatures on timing integrity. In LATW 2011 - 12th IEEE Latin-American Test Workshop [5985920] (LATW 2011 - 12th IEEE Latin-American Test Workshop). https://doi.org/10.1109/LATW.2011.5985920