Qpace: Power-efficient parallel architecture based on IBM PowerXCell 8i

H. Baier, H. Boettiger, M. Drochner, N. Eicker, U. Fischer, Z. Fodor, A. Frommer, C. Gomez, G. Goldrian, S. Heybrock, D. Hierl, M. Hüsken, T. Huth, B. Krill, J. Lauritsen, T. Lippert, T. Maurer, B. Mendl, N. Meyer, A. NobileI. Ouda, M. Pivanti, D. Pleiter, M. Ries, A. Schäfer, H. Schick, F. Schifano, H. Simma, S. Solbrig, T. Streuer, K. H. Sulanke, R. Tripiccione, J. S. Vogt, T. Wettig, F. Winter

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. Each node comprises an IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The architecture was systematically optimized with respect to power consumption. This put QPACE in the number one spot on the Green500 List published in November 2009. In this paper we give an overview of the architecture and highlight the steps taken to improve power efficiency.

Original languageEnglish
Pages (from-to)149-154
Number of pages6
JournalComputer Science - Research and Development
Volume25
Issue number3-4
DOIs
Publication statusPublished - Jan 1 2010

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Keywords

  • Parallel architectures
  • Special-purpose and application-based systems

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Baier, H., Boettiger, H., Drochner, M., Eicker, N., Fischer, U., Fodor, Z., Frommer, A., Gomez, C., Goldrian, G., Heybrock, S., Hierl, D., Hüsken, M., Huth, T., Krill, B., Lauritsen, J., Lippert, T., Maurer, T., Mendl, B., Meyer, N., ... Winter, F. (2010). Qpace: Power-efficient parallel architecture based on IBM PowerXCell 8i. Computer Science - Research and Development, 25(3-4), 149-154. https://doi.org/10.1007/s00450-010-0122-4