Regarding thermal issues in digital IC design a major concern is how timing integrity is affected by the elevated junction temperature and temperature gradients on the chip surface. To predict this in a thermal aware design process one needs a dedicated simulation tool in which the logic simulation of the circuit is coupled to the thermal simulation of the chip and its environment. This paper presents two approaches to this so called logi-thermal simulation. In one of our approaches we rely completely on industry standard EDA tools, standard EDA file formats and interfaces. In the other solution which provides us total freedom in the abstraction level of circuit description and simulation accuracy we use our own logic simulation engine. In both cases the logic simulation engine is connected to our own thermal simulation engines which also use compact thermal models of the IC package during simulation. This paper describes certain implementation aspects and features of our logi-thermal simulation solutions, with emphasizes on modeling the thermal properties of the IC packaging.