Makyoh-topography assessment of etch and polish removal of processed circuits for substrate re-use

István E. Lukács, Ferenc Riesz

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A Makyoh-topography study of the removal of processed Si circuits by etching and lapping/polishing for substrate re-use is reported. Removal of the individual circuit layers (oxide, metal) causes a uniform change in the overall wafer curvature, corresponding to strain release. Lapping/polishing removes the undulation that is originally present but introduces a new one that is characteristic of the imperfection of the polishing process.

Original languageEnglish
Pages (from-to)380-386
Number of pages7
JournalMicroelectronic Engineering
Volume65
Issue number4
DOIs
Publication statusPublished - May 1 2003

Keywords

  • Makyoh topography
  • Surface flatness
  • Wafer reclaim

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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