Limits to binary logic switch scaling - A gedanken model

Victor V. Zhirnov, Ralph K. Cavin, James A. Hutchby, George I. Bourianoff

Research output: Contribution to journalArticle

351 Citations (Scopus)


In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation. "We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.

Original languageEnglish
Pages (from-to)1934-1939
Number of pages6
JournalProceedings of the IEEE
Issue number11
Publication statusPublished - Nov 2003


  • Closely packed devices
  • Device scaling limits
  • Digital integrated circuits
  • Heat removal
  • Nanotechnology
  • Power consumption
  • Tunneling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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