IDDQ testing of submicron CMOS - by cooling?

M. Rencz, V. Székely, S. Török, K. Torki, B. Courtois

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

The usability of IDDQ testing is limited by the subthreshold currents of the low-VT, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of -75...25 Centigrade. The subthreshold currents decrease by a factor of about 100-1000 by cooling-down the chip to -75 Centigrade.

Original languageEnglish
Pages (from-to)453-461
Number of pages9
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume16
Issue number5
DOIs
Publication statusPublished - Oct 2000

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Cooling
Testing
MOSFET devices
Bias voltage
Threshold voltage
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

IDDQ testing of submicron CMOS - by cooling? / Rencz, M.; Székely, V.; Török, S.; Torki, K.; Courtois, B.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 5, 10.2000, p. 453-461.

Research output: Contribution to journalArticle

Rencz, M. ; Székely, V. ; Török, S. ; Torki, K. ; Courtois, B. / IDDQ testing of submicron CMOS - by cooling?. In: Journal of Electronic Testing: Theory and Applications (JETTA). 2000 ; Vol. 16, No. 5. pp. 453-461.
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