Issues in junction-to-case thermal characterization of power packages with large surface area

Andras Vass-Varnai, Shan Gao, Zoltan Sarkany, Jongman Kim, Seogmoon Choi, Gabor Farkas, A. Poppe, M. Rencz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces [1,2]. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.

Original languageEnglish
Title of host publicationAnnual IEEE Semiconductor Thermal Measurement and Management Symposium
Pages158-164
Number of pages7
DOIs
Publication statusPublished - 2010
Event26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2010 - Santa Clara, CA, United States
Duration: Feb 21 2010Feb 25 2010

Other

Other26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2010
CountryUnited States
CitySanta Clara, CA
Period2/21/102/25/10

Fingerprint

heat transmission
Heat transfer
chips
Heating
modules
Insulated gate bipolar transistors (IGBT)
Thermal cycling
Heat resistance
heating
thermal resistance
Cracks
cracks
Testing
heat
cycles
Hot Temperature
causes
simulation

Keywords

  • Dual interface methodology
  • Junction-to-case thermal resistance
  • Large substrate area power modules
  • Thermal transient testing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Vass-Varnai, A., Gao, S., Sarkany, Z., Kim, J., Choi, S., Farkas, G., ... Rencz, M. (2010). Issues in junction-to-case thermal characterization of power packages with large surface area. In Annual IEEE Semiconductor Thermal Measurement and Management Symposium (pp. 158-164). [5444299] https://doi.org/10.1109/STHERM.2010.5444299

Issues in junction-to-case thermal characterization of power packages with large surface area. / Vass-Varnai, Andras; Gao, Shan; Sarkany, Zoltan; Kim, Jongman; Choi, Seogmoon; Farkas, Gabor; Poppe, A.; Rencz, M.

Annual IEEE Semiconductor Thermal Measurement and Management Symposium. 2010. p. 158-164 5444299.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vass-Varnai, A, Gao, S, Sarkany, Z, Kim, J, Choi, S, Farkas, G, Poppe, A & Rencz, M 2010, Issues in junction-to-case thermal characterization of power packages with large surface area. in Annual IEEE Semiconductor Thermal Measurement and Management Symposium., 5444299, pp. 158-164, 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2010, Santa Clara, CA, United States, 2/21/10. https://doi.org/10.1109/STHERM.2010.5444299
Vass-Varnai A, Gao S, Sarkany Z, Kim J, Choi S, Farkas G et al. Issues in junction-to-case thermal characterization of power packages with large surface area. In Annual IEEE Semiconductor Thermal Measurement and Management Symposium. 2010. p. 158-164. 5444299 https://doi.org/10.1109/STHERM.2010.5444299
Vass-Varnai, Andras ; Gao, Shan ; Sarkany, Zoltan ; Kim, Jongman ; Choi, Seogmoon ; Farkas, Gabor ; Poppe, A. ; Rencz, M. / Issues in junction-to-case thermal characterization of power packages with large surface area. Annual IEEE Semiconductor Thermal Measurement and Management Symposium. 2010. pp. 158-164
@inproceedings{3526a665989b4e359da10de2934088f7,
title = "Issues in junction-to-case thermal characterization of power packages with large surface area",
abstract = "There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces [1,2]. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.",
keywords = "Dual interface methodology, Junction-to-case thermal resistance, Large substrate area power modules, Thermal transient testing",
author = "Andras Vass-Varnai and Shan Gao and Zoltan Sarkany and Jongman Kim and Seogmoon Choi and Gabor Farkas and A. Poppe and M. Rencz",
year = "2010",
doi = "10.1109/STHERM.2010.5444299",
language = "English",
isbn = "9781424464586",
pages = "158--164",
booktitle = "Annual IEEE Semiconductor Thermal Measurement and Management Symposium",

}

TY - GEN

T1 - Issues in junction-to-case thermal characterization of power packages with large surface area

AU - Vass-Varnai, Andras

AU - Gao, Shan

AU - Sarkany, Zoltan

AU - Kim, Jongman

AU - Choi, Seogmoon

AU - Farkas, Gabor

AU - Poppe, A.

AU - Rencz, M.

PY - 2010

Y1 - 2010

N2 - There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces [1,2]. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.

AB - There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces [1,2]. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.

KW - Dual interface methodology

KW - Junction-to-case thermal resistance

KW - Large substrate area power modules

KW - Thermal transient testing

UR - http://www.scopus.com/inward/record.url?scp=77952649606&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77952649606&partnerID=8YFLogxK

U2 - 10.1109/STHERM.2010.5444299

DO - 10.1109/STHERM.2010.5444299

M3 - Conference contribution

AN - SCOPUS:77952649606

SN - 9781424464586

SP - 158

EP - 164

BT - Annual IEEE Semiconductor Thermal Measurement and Management Symposium

ER -