Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm

Z. Kincses, Zs Vörösházi, Z. Nagy, P. Szolgay, T. Laviniu, A. Gacsádi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper an image correlation algorithm is implemented on FPGA architecture for assisted movements of visually impaired persons or automotive driving systems. Taking into account the limitations of FPGA devices and the special requirements of the correlation based image matching algorithm a semi-parallel approach is proposed. This provides an optimal tradeoff between area and speed of the implemented algorithm. Several key issues are investigated and discussed related to the speed and area.

Original languageEnglish
Title of host publication2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
DOIs
Publication statusPublished - Dec 13 2012
Event2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 - Turin, Italy
Duration: Aug 29 2012Aug 29 2012

Publication series

NameInternational Workshop on Cellular Nanoscale Networks and their Applications
ISSN (Print)2165-0160
ISSN (Electronic)2165-0179

Other

Other2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
CountryItaly
CityTurin
Period8/29/128/29/12

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ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Kincses, Z., Vörösházi, Z., Nagy, Z., Szolgay, P., Laviniu, T., & Gacsádi, A. (2012). Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm. In 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 [6331455] (International Workshop on Cellular Nanoscale Networks and their Applications). https://doi.org/10.1109/CNNA.2012.6331455