Integrating on-chip temperature sensors into DfT schemes and BIST architectures

V. Szekely, M. Rencz, B. Courtois

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Abstract

The continuously increasing power densities in integrated circuits necessitated the introduction of DfTT (Design for Thermal Testability) design methodology to prevent overheating effects. Newly developed CMOS temperature sensors enable the application of DfTT principle in safety-critical circuits. Parameters and operation principles of the low-power small-area temperature sensor family are presented in details in the paper, followed by the discussion of placement and testing strategies.

Original languageEnglish
Pages440-445
Number of pages6
Publication statusPublished - Jan 1 1997
EventProceedings of the 1997 15th VLSI Test Symposium - Monterey, CA, USA
Duration: Apr 27 1997May 1 1997

Other

OtherProceedings of the 1997 15th VLSI Test Symposium
CityMonterey, CA, USA
Period4/27/975/1/97

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ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Szekely, V., Rencz, M., & Courtois, B. (1997). Integrating on-chip temperature sensors into DfT schemes and BIST architectures. 440-445. Paper presented at Proceedings of the 1997 15th VLSI Test Symposium, Monterey, CA, USA, .