Implementation of embedded emulated-digital CNN-UM global analogic programming unit on FPGA and its application

Zsolt Vörösházi, András Kiss, Zoltan Nagy, P. Szolgay

Research output: Contribution to journalArticle

26 Citations (Scopus)

Abstract

The paper addresses the issue of implementing an embedded global analogic programming unit (GAPU) on the reconfigurable emulated-digital cellular neural/nonlinear networks universal machine (CNN-UM) architecture that has been extended by a flexible Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi-i vision systems. The quality of the embedded GAPU implementation is demonstrated by an analogic algorithm, in which sequences of template operations are required. Based on the experiments, several important issues relating to the acceleration efficiency, accuracy, cell size, and area consumption are discussed and compared with different CNN-UM implementations.

Original languageEnglish
Pages (from-to)589-603
Number of pages15
JournalInternational Journal of Circuit Theory and Applications
Volume36
Issue number5-6
DOIs
Publication statusPublished - Jul 2008

Fingerprint

Nonlinear networks
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Programming
Unit
Microprocessor chips
Cell Size
Microprocessor
Vision System
Template
High Speed
Computing
Experiments
Experiment

Keywords

  • Analogic algorithm
  • CNN-UM
  • Embedded GAPU
  • FPGA
  • MicroBlaze soft processor core

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Implementation of embedded emulated-digital CNN-UM global analogic programming unit on FPGA and its application. / Vörösházi, Zsolt; Kiss, András; Nagy, Zoltan; Szolgay, P.

In: International Journal of Circuit Theory and Applications, Vol. 36, No. 5-6, 07.2008, p. 589-603.

Research output: Contribution to journalArticle

@article{3a945e2ea9354c8ab8b99f1f0d2024f5,
title = "Implementation of embedded emulated-digital CNN-UM global analogic programming unit on FPGA and its application",
abstract = "The paper addresses the issue of implementing an embedded global analogic programming unit (GAPU) on the reconfigurable emulated-digital cellular neural/nonlinear networks universal machine (CNN-UM) architecture that has been extended by a flexible Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi-i vision systems. The quality of the embedded GAPU implementation is demonstrated by an analogic algorithm, in which sequences of template operations are required. Based on the experiments, several important issues relating to the acceleration efficiency, accuracy, cell size, and area consumption are discussed and compared with different CNN-UM implementations.",
keywords = "Analogic algorithm, CNN-UM, Embedded GAPU, FPGA, MicroBlaze soft processor core",
author = "Zsolt V{\"o}r{\"o}sh{\'a}zi and Andr{\'a}s Kiss and Zoltan Nagy and P. Szolgay",
year = "2008",
month = "7",
doi = "10.1002/cta.507",
language = "English",
volume = "36",
pages = "589--603",
journal = "International Journal of Circuit Theory and Applications",
issn = "0098-9886",
publisher = "John Wiley and Sons Ltd",
number = "5-6",

}

TY - JOUR

T1 - Implementation of embedded emulated-digital CNN-UM global analogic programming unit on FPGA and its application

AU - Vörösházi, Zsolt

AU - Kiss, András

AU - Nagy, Zoltan

AU - Szolgay, P.

PY - 2008/7

Y1 - 2008/7

N2 - The paper addresses the issue of implementing an embedded global analogic programming unit (GAPU) on the reconfigurable emulated-digital cellular neural/nonlinear networks universal machine (CNN-UM) architecture that has been extended by a flexible Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi-i vision systems. The quality of the embedded GAPU implementation is demonstrated by an analogic algorithm, in which sequences of template operations are required. Based on the experiments, several important issues relating to the acceleration efficiency, accuracy, cell size, and area consumption are discussed and compared with different CNN-UM implementations.

AB - The paper addresses the issue of implementing an embedded global analogic programming unit (GAPU) on the reconfigurable emulated-digital cellular neural/nonlinear networks universal machine (CNN-UM) architecture that has been extended by a flexible Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi-i vision systems. The quality of the embedded GAPU implementation is demonstrated by an analogic algorithm, in which sequences of template operations are required. Based on the experiments, several important issues relating to the acceleration efficiency, accuracy, cell size, and area consumption are discussed and compared with different CNN-UM implementations.

KW - Analogic algorithm

KW - CNN-UM

KW - Embedded GAPU

KW - FPGA

KW - MicroBlaze soft processor core

UR - http://www.scopus.com/inward/record.url?scp=47749123863&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=47749123863&partnerID=8YFLogxK

U2 - 10.1002/cta.507

DO - 10.1002/cta.507

M3 - Article

VL - 36

SP - 589

EP - 603

JO - International Journal of Circuit Theory and Applications

JF - International Journal of Circuit Theory and Applications

SN - 0098-9886

IS - 5-6

ER -