How to measure perfectness of parallelization in hardware/software systems

János Végh, P. Molnár

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

After that single-thread processing performance has stalled more than a decade ago, research has intensified in direction of using more intensive parallelism. Unfortunately, the resulting computer performance is not simply the sum of single processor performances of individual processors working in parallel. Communication, housekeeping and some inherently sequential code parts degrade efficiency of parallelization, in a strongly nonlinear way. Amdahl's law provides an upper bound for achievable parallelism, but it requires the exact knowledge of the structure of the program, and in addition, it can consider realistic systems in a rather limited way. Modifying Amdahl's law for considering modern general purpose systems working in parallel, and reverting the formula derived, a quantitative merit was delivered, which shows how perfect the result of parallelization is. The derived formulas are applied to problems on different fields, like qualifying efficacy of a load balancing compiler, comparing communication methods usable in an SoC system, or finding out which law governed the supercomputer technology in the past quarter of century.

Original languageEnglish
Title of host publication2017 18th International Carpathian Control Conference, ICCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages394-399
Number of pages6
ISBN (Electronic)9781509048625
DOIs
Publication statusPublished - Jul 6 2017
Event18th International Carpathian Control Conference, ICCC 2017 - Sinaia, Romania
Duration: May 28 2017May 31 2017

Other

Other18th International Carpathian Control Conference, ICCC 2017
CountryRomania
CitySinaia
Period5/28/175/31/17

Fingerprint

Parallelization
Software System
Hardware
Parallelism
Supercomputers
Communication
Resource allocation
Supercomputer
Load Balancing
Compiler
Thread
Efficacy
Processing
Upper bound
System-on-chip
Knowledge

Keywords

  • computational efficiency
  • load balancing
  • parallelism
  • performance measurement
  • SoC performance
  • supercomputer performance

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Science Applications
  • Control and Systems Engineering
  • Control and Optimization

Cite this

Végh, J., & Molnár, P. (2017). How to measure perfectness of parallelization in hardware/software systems. In 2017 18th International Carpathian Control Conference, ICCC 2017 (pp. 394-399). [7970432] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CarpathianCC.2017.7970432

How to measure perfectness of parallelization in hardware/software systems. / Végh, János; Molnár, P.

2017 18th International Carpathian Control Conference, ICCC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 394-399 7970432.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Végh, J & Molnár, P 2017, How to measure perfectness of parallelization in hardware/software systems. in 2017 18th International Carpathian Control Conference, ICCC 2017., 7970432, Institute of Electrical and Electronics Engineers Inc., pp. 394-399, 18th International Carpathian Control Conference, ICCC 2017, Sinaia, Romania, 5/28/17. https://doi.org/10.1109/CarpathianCC.2017.7970432
Végh J, Molnár P. How to measure perfectness of parallelization in hardware/software systems. In 2017 18th International Carpathian Control Conference, ICCC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 394-399. 7970432 https://doi.org/10.1109/CarpathianCC.2017.7970432
Végh, János ; Molnár, P. / How to measure perfectness of parallelization in hardware/software systems. 2017 18th International Carpathian Control Conference, ICCC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 394-399
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