How to avoid false lock in SPLL frequency synthesizers

Z. Szabó, G. Kolumbán

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In addition to the stable fixed point which should be achieved under steady-state conditions, the Sampling Phase-Locked Loop (SPLL) implemented with a loop filter has another stable attractor in which an unwanted periodic solution, called false lock, develops in the loop. After the acquisition process, the SPLL either reaches the desired fixed point or gets into false lock, depending on the initial conditions. SPLLs are frequently used in measurement equipment to implement frequency synthesizers and oscillators with high spectral purity and stability. False lock results in a measurement error which has to be avoided. The main goal of this paper is to give a model for the false lock phenomenon which explains how the system gets into false lock. The theoretical results have been verified by measurements. Based on the theoretical results, a simple circuit configuration has been developed which reduces the time constant of the loop filter for acquisition and so prevents false lock.

Original languageEnglish
Title of host publicationConference Record - IEEE Instrumentation and Measurement Technology Conference
Pages738-743
Number of pages6
Volume2
Publication statusPublished - 2001
Event18th IEEE Instrumentation and Measurement of Informatics -Rediscovering Measurement in the Age of Informatics - Budapest, Hungary
Duration: May 21 2001May 23 2001

Other

Other18th IEEE Instrumentation and Measurement of Informatics -Rediscovering Measurement in the Age of Informatics
CountryHungary
CityBudapest
Period5/21/015/23/01

Fingerprint

frequency synthesizers
Frequency synthesizers
Phase locked loops
sampling
Sampling
Measurement errors
Networks (circuits)
acquisition
filters
time constant
purity
oscillators
configurations

Keywords

  • Coexisting attractors
  • False lock
  • Frequency synthesizer
  • Sampling phase-locked loop
  • Unwanted periodic orbit

ASJC Scopus subject areas

  • Instrumentation

Cite this

Szabó, Z., & Kolumbán, G. (2001). How to avoid false lock in SPLL frequency synthesizers. In Conference Record - IEEE Instrumentation and Measurement Technology Conference (Vol. 2, pp. 738-743)

How to avoid false lock in SPLL frequency synthesizers. / Szabó, Z.; Kolumbán, G.

Conference Record - IEEE Instrumentation and Measurement Technology Conference. Vol. 2 2001. p. 738-743.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Szabó, Z & Kolumbán, G 2001, How to avoid false lock in SPLL frequency synthesizers. in Conference Record - IEEE Instrumentation and Measurement Technology Conference. vol. 2, pp. 738-743, 18th IEEE Instrumentation and Measurement of Informatics -Rediscovering Measurement in the Age of Informatics, Budapest, Hungary, 5/21/01.
Szabó Z, Kolumbán G. How to avoid false lock in SPLL frequency synthesizers. In Conference Record - IEEE Instrumentation and Measurement Technology Conference. Vol. 2. 2001. p. 738-743
Szabó, Z. ; Kolumbán, G. / How to avoid false lock in SPLL frequency synthesizers. Conference Record - IEEE Instrumentation and Measurement Technology Conference. Vol. 2 2001. pp. 738-743
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