Enhanced emulated digital CNN-UM (CASTLE) arithmetic cores

Timót Hidvégi, Péter Keresztes, Péter Szolgay

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

An emulated digital CNN-UM (CASTLE) architecture was published few years ago.1 Different emulated digital CNN-UM architectures are analyzed in the paper. These new modified architectures are optimized according to the silicon area, operating speed or dissipated power. A reconfigurable arithmetic core will also be shown in the paper, by which solution of the neighborhood size can be changed. An advanced CASTLE with pipe-lining is presented. The operation frequency is increased by using this solution in approximately 10 times.

Original languageEnglish
Pages (from-to)711-738
Number of pages28
JournalJournal of Circuits, Systems and Computers
Volume12
Issue number6
DOIs
Publication statusPublished - Dec 2003

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Pipe linings
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Keywords

  • Cellular nonlinear/neural networks (CNN)
  • CNN Universal Machine
  • Emulated digital architecture
  • Optimized arithmetic core

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Enhanced emulated digital CNN-UM (CASTLE) arithmetic cores. / Hidvégi, Timót; Keresztes, Péter; Szolgay, Péter.

In: Journal of Circuits, Systems and Computers, Vol. 12, No. 6, 12.2003, p. 711-738.

Research output: Contribution to journalArticle

Hidvégi, Timót ; Keresztes, Péter ; Szolgay, Péter. / Enhanced emulated digital CNN-UM (CASTLE) arithmetic cores. In: Journal of Circuits, Systems and Computers. 2003 ; Vol. 12, No. 6. pp. 711-738.
@article{e97f069c022943a586ab3c997d2890e2,
title = "Enhanced emulated digital CNN-UM (CASTLE) arithmetic cores",
abstract = "An emulated digital CNN-UM (CASTLE) architecture was published few years ago.1 Different emulated digital CNN-UM architectures are analyzed in the paper. These new modified architectures are optimized according to the silicon area, operating speed or dissipated power. A reconfigurable arithmetic core will also be shown in the paper, by which solution of the neighborhood size can be changed. An advanced CASTLE with pipe-lining is presented. The operation frequency is increased by using this solution in approximately 10 times.",
keywords = "Cellular nonlinear/neural networks (CNN), CNN Universal Machine, Emulated digital architecture, Optimized arithmetic core",
author = "Tim{\'o}t Hidv{\'e}gi and P{\'e}ter Keresztes and P{\'e}ter Szolgay",
year = "2003",
month = "12",
doi = "10.1142/S0218126603001136",
language = "English",
volume = "12",
pages = "711--738",
journal = "Journal of Circuits, Systems and Computers",
issn = "0218-1266",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "6",

}

TY - JOUR

T1 - Enhanced emulated digital CNN-UM (CASTLE) arithmetic cores

AU - Hidvégi, Timót

AU - Keresztes, Péter

AU - Szolgay, Péter

PY - 2003/12

Y1 - 2003/12

N2 - An emulated digital CNN-UM (CASTLE) architecture was published few years ago.1 Different emulated digital CNN-UM architectures are analyzed in the paper. These new modified architectures are optimized according to the silicon area, operating speed or dissipated power. A reconfigurable arithmetic core will also be shown in the paper, by which solution of the neighborhood size can be changed. An advanced CASTLE with pipe-lining is presented. The operation frequency is increased by using this solution in approximately 10 times.

AB - An emulated digital CNN-UM (CASTLE) architecture was published few years ago.1 Different emulated digital CNN-UM architectures are analyzed in the paper. These new modified architectures are optimized according to the silicon area, operating speed or dissipated power. A reconfigurable arithmetic core will also be shown in the paper, by which solution of the neighborhood size can be changed. An advanced CASTLE with pipe-lining is presented. The operation frequency is increased by using this solution in approximately 10 times.

KW - Cellular nonlinear/neural networks (CNN)

KW - CNN Universal Machine

KW - Emulated digital architecture

KW - Optimized arithmetic core

UR - http://www.scopus.com/inward/record.url?scp=2442562486&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2442562486&partnerID=8YFLogxK

U2 - 10.1142/S0218126603001136

DO - 10.1142/S0218126603001136

M3 - Article

AN - SCOPUS:2442562486

VL - 12

SP - 711

EP - 738

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

SN - 0218-1266

IS - 6

ER -