Efficient method for the self-consistent electro-thermal simulation and its integration into a CAD framework

V. Szekely, A. Poppe, M. Rencz, G. Farkas, A. Csendes, A. Pahi

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

In this paper we address the chip-level thermal simulation problem. Our work is based on some early results treating electro-thermal problems on circuit level. The developed electro-thermal simulation package has been integrated under Cadence DFWII (Opus). Due to its relatively low CPU need this package can be used as a thermal verification tool of layouts of analog circuits.

Original languageEnglish
Number of pages1
JournalProceedings of European Design and Test Conference
Publication statusPublished - Jan 1 1996
EventProceedings of the 1996 European Design & Test Conference - Paris, Fr
Duration: Mar 11 1996Mar 14 1996

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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