### Abstract

The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 10^{9} XPS for a single chip operation with an effective area of 0.379 cm^{2} and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.

Original language | English |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |

Publisher | IEEE |

Pages | 135-138 |

Number of pages | 4 |

Volume | 4 |

Publication status | Published - 1994 |

Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994 |

### Other

Other | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) |
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City | London, England |

Period | 5/30/94 → 6/2/94 |

### Fingerprint

### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials

### Cite this

*Proceedings - IEEE International Symposium on Circuits and Systems*(Vol. 4, pp. 135-138). IEEE.

**Current-mode DTCNN universal chip.** / Harrer, Hubert; Nossek, Josef A.; Roska, T.; Chua, Leon O.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - IEEE International Symposium on Circuits and Systems.*vol. 4, IEEE, pp. 135-138, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), London, England, 5/30/94.

}

TY - GEN

T1 - Current-mode DTCNN universal chip

AU - Harrer, Hubert

AU - Nossek, Josef A.

AU - Roska, T.

AU - Chua, Leon O.

PY - 1994

Y1 - 1994

N2 - The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 109 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.

AB - The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 109 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.

UR - http://www.scopus.com/inward/record.url?scp=0028573192&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028573192&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028573192

VL - 4

SP - 135

EP - 138

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -