Current-mode DTCNN universal chip

Hubert Harrer, Josef A. Nossek, T. Roska, Leon O. Chua

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Citations (Scopus)

Abstract

The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 109 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages135-138
Number of pages4
Volume4
Publication statusPublished - 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

Other

OtherProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
CityLondon, England
Period5/30/946/2/94

Fingerprint

Cellular neural networks
SPICE
Clocks
Electric power utilization
X ray photoelectron spectroscopy
Feedback
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Harrer, H., Nossek, J. A., Roska, T., & Chua, L. O. (1994). Current-mode DTCNN universal chip. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 135-138). IEEE.

Current-mode DTCNN universal chip. / Harrer, Hubert; Nossek, Josef A.; Roska, T.; Chua, Leon O.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 IEEE, 1994. p. 135-138.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harrer, H, Nossek, JA, Roska, T & Chua, LO 1994, Current-mode DTCNN universal chip. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 4, IEEE, pp. 135-138, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), London, England, 5/30/94.
Harrer H, Nossek JA, Roska T, Chua LO. Current-mode DTCNN universal chip. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4. IEEE. 1994. p. 135-138
Harrer, Hubert ; Nossek, Josef A. ; Roska, T. ; Chua, Leon O. / Current-mode DTCNN universal chip. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 IEEE, 1994. pp. 135-138
@inproceedings{46b47821dcbb47acab6aab8964d3c208,
title = "Current-mode DTCNN universal chip",
abstract = "The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 109 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.",
author = "Hubert Harrer and Nossek, {Josef A.} and T. Roska and Chua, {Leon O.}",
year = "1994",
language = "English",
volume = "4",
pages = "135--138",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "IEEE",

}

TY - GEN

T1 - Current-mode DTCNN universal chip

AU - Harrer, Hubert

AU - Nossek, Josef A.

AU - Roska, T.

AU - Chua, Leon O.

PY - 1994

Y1 - 1994

N2 - The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 109 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.

AB - The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 μm process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 μm by 425 μm and the simulated speed is between 1MHz and 10MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 109 XPS for a single chip operation with an effective area of 0.379 cm2 and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.

UR - http://www.scopus.com/inward/record.url?scp=0028573192&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028573192&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028573192

VL - 4

SP - 135

EP - 138

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -