A reduction of the VDD voltage, and thus the threshold voltage, in submicrometre CMOS circuits, results in an increase in the subthreshold current of the transistors and, consequently, in an increase in the overall quiescent current. This effect prohibits the use of IDDQ testing. Based on experimental investigation into the subthreshold characteristics of deep submicrometre transistors, the authors propose a cooling of the circuit under test as a method to reduce these difficulties.
- Circuit testing
ASJC Scopus subject areas
- Electrical and Electronic Engineering