Configurable multi-layer CNN-UM emulator on FPGA using distributed arithmetic

Zoltán Nagy, Péter Szolgay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A new emulated digital multi-layer CNN-UM chip architecture called Falcon has been developed. Simulation runtimes can be hundred times shorter using the Falcon processor array compared to the software simulation. This huge computing power makes real time image processing possible. In this paper the main steps of the FPGA implementation and optimization are introduced. The Distributed Arithmetic technique is used to optimize the architecture on FPGAs. Using this technique, smaller and faster arithmetic units can be designed than the conventional approach where multiplier cores and adder trees are used to compute the state equation of the CNN array.

Original languageEnglish
Title of host publicationICECS 2002 - 9th IEEE International Conference on Electronics, Circuits and Systems
Pages1251-1254
Number of pages4
DOIs
Publication statusPublished - Dec 1 2002
Event9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002 - Dubrovnik, Croatia
Duration: Sep 15 2002Sep 18 2002

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3

Other

Other9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002
CountryCroatia
CityDubrovnik
Period9/15/029/18/02

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Nagy, Z., & Szolgay, P. (2002). Configurable multi-layer CNN-UM emulator on FPGA using distributed arithmetic. In ICECS 2002 - 9th IEEE International Conference on Electronics, Circuits and Systems (pp. 1251-1254). [1046481] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3). https://doi.org/10.1109/ICECS.2002.1046481