Abstract
ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.
| Original language | English |
|---|---|
| Journal | Proceedings of Science |
| Volume | 2017-September |
| Publication status | Published - Jan 1 2017 |
| Event | 2017 Topical Workshop on Electronics for Particle Physics, TWEPP 2017 - Santa Cruz, United States Duration: Sep 11 2017 → Sep 14 2017 |
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ASJC Scopus subject areas
- General
Cite this
Clock and trigger distribution for ALICE using the CRU FPGA card. / Imrek, J.
In: Proceedings of Science, Vol. 2017-September, 01.01.2017.Research output: Contribution to journal › Conference article
}
TY - JOUR
T1 - Clock and trigger distribution for ALICE using the CRU FPGA card
AU - Imrek, J.
PY - 2017/1/1
Y1 - 2017/1/1
N2 - ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.
AB - ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.
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UR - http://www.scopus.com/inward/citedby.url?scp=85050459721&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:85050459721
VL - 2017-September
JO - Proceedings of Science
JF - Proceedings of Science
SN - 1824-8039
ER -