Clock and trigger distribution for ALICE using the CRU FPGA card

Research output: Contribution to journalConference article

Abstract

ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.

Original languageEnglish
JournalProceedings of Science
Volume2017-September
Publication statusPublished - Jan 1 2017
Event2017 Topical Workshop on Electronics for Particle Physics, TWEPP 2017 - Santa Cruz, United States
Duration: Sep 11 2017Sep 14 2017

Fingerprint

cards
clocks
readout
upgrading
actuators
time measurement
vibration
cleaners
distributing
hardware
requirements
physics
electronics

ASJC Scopus subject areas

  • General

Cite this

Clock and trigger distribution for ALICE using the CRU FPGA card. / Imrek, J.

In: Proceedings of Science, Vol. 2017-September, 01.01.2017.

Research output: Contribution to journalConference article

@article{c75c40145d4341cfb8a9fd30e3359a42,
title = "Clock and trigger distribution for ALICE using the CRU FPGA card",
abstract = "ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.",
author = "J. Imrek",
year = "2017",
month = "1",
day = "1",
language = "English",
volume = "2017-September",
journal = "Proceedings of Science",
issn = "1824-8039",
publisher = "Sissa Medialab Srl",

}

TY - JOUR

T1 - Clock and trigger distribution for ALICE using the CRU FPGA card

AU - Imrek, J.

PY - 2017/1/1

Y1 - 2017/1/1

N2 - ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.

AB - ALICE is preparing a major upgrade for 2021. Subdetectors upgrading their DAQ electronics will use a common hardware to receive physics data: the Common Readout Unit (CRU). The same CRU will also distribute the LHC clock and trigger to many of the upgrading subdetectors (to 7800 front end cards). Requirements are strict: for the clock the allowed jitter (RMS) is typically <300ps, and <20ps for timing critical subdetectors; the allowed variation of skew is typically <1ns, and <100ps for timing critical subdetectors. A constant latency for distributing the trigger is essential. A novel approach to implement clock forwarding – using only the internal PLLs of the CRU’s onboard FPGA, without using an external jitter cleaner PLL – is presented.

UR - http://www.scopus.com/inward/record.url?scp=85050459721&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85050459721&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:85050459721

VL - 2017-September

JO - Proceedings of Science

JF - Proceedings of Science

SN - 1824-8039

ER -