### Abstract

Cellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology. In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary-valued. A highly efficient CMOS-compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.

Original language | English |
---|---|

Pages (from-to) | 533-553 |

Number of pages | 21 |

Journal | International Journal of Circuit Theory and Applications |

Volume | 20 |

Issue number | 5 |

Publication status | Published - Sep 1992 |

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### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*International Journal of Circuit Theory and Applications*,

*20*(5), 533-553.

**Cellular neural networks : Theory and circuit design.** / Nossek, Josef A.; Seiler, Gerhard; Roska, T.; Chua, Leon O.

Research output: Contribution to journal › Article

*International Journal of Circuit Theory and Applications*, vol. 20, no. 5, pp. 533-553.

}

TY - JOUR

T1 - Cellular neural networks

T2 - Theory and circuit design

AU - Nossek, Josef A.

AU - Seiler, Gerhard

AU - Roska, T.

AU - Chua, Leon O.

PY - 1992/9

Y1 - 1992/9

N2 - Cellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology. In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary-valued. A highly efficient CMOS-compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.

AB - Cellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology. In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary-valued. A highly efficient CMOS-compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.

UR - http://www.scopus.com/inward/record.url?scp=0026915218&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026915218&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0026915218

VL - 20

SP - 533

EP - 553

JO - International Journal of Circuit Theory and Applications

JF - International Journal of Circuit Theory and Applications

SN - 0098-9886

IS - 5

ER -