Castle: An emulated digital CNN architecture; design issues, new results

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A new emulated digital CNN Universal Machine chip architecture is introduced in this paper. The chip contains 24 CNN core processors using 70mm2 silicon area with a 0.35 μm technology. Its speed is Ins/virtual cells/CNN iterations with 12 bits precision. This enables to execute over five hundred 3×3 convolutions on each frame of a 240×320 sized 25fps (standard NTSC) digital image flow. Another new feature of the design is the different precision capability. This allows the user to convert precision to speed.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages199-202
Number of pages4
ISBN (Electronic)0780350081
DOIs
Publication statusPublished - Jan 1 1998
Event5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal
Duration: Sep 7 1998Sep 10 1998

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Conference

Conference5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
CountryPortugal
CityLisboa
Period9/7/989/10/98

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Engineering(all)

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  • Cite this

    Zarándy, Á., Keresztes, P., Roska, T., & Szolgay, P. (1998). Castle: An emulated digital CNN architecture; design issues, new results. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 199-202). [813303] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1998.813303