Automatic generation of locally controlled arithmetic unit via floorplan based partitioning

Csaba Nemes, Zoltán Nagy, Péter Szolgay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In the paper a framework for generating a locally controlled arithmetic unit is presented including graph generation from a mathematical expression, graph partitioning to determine locally controlled parts of the design and VHDL generation. The output of the framework is a pipelined architecture containing locally controlled groups of floating point units. It is demonstrated that both partitioning and placement aspects of the design have to be considered to obtain a highspeed circuit. In a well-placeable design locally controlled groups can be mapped to FPGA in such a way that only neighboring groups communicate with each other. In the presented algorithm an initial floorplan of the floating point units is produced and a novel graph partitioning representation is used for partitioning the floating point units to obtain a well-placeable design. The framework is demonstrated during the automatic circuit generation of a complex mathematical expression related to Computation Fluid Dynamics (CFD). The framework produces 15-27% faster design than the unpartitioned, globally controlled one in the price of a modest area increase. The framework automatically produces well-placeable deadlock-free partitions for complex expressions as well, while in case of traditional partitioners these objectives cannot be targeted.

Original languageEnglish
Title of host publication2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
DOIs
Publication statusPublished - Dec 13 2012
Event2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 - Turin, Italy
Duration: Aug 29 2012Aug 29 2012

Publication series

NameInternational Workshop on Cellular Nanoscale Networks and their Applications
ISSN (Print)2165-0160
ISSN (Electronic)2165-0179

Other

Other2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
CountryItaly
CityTurin
Period8/29/128/29/12

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Automatic generation of locally controlled arithmetic unit via floorplan based partitioning'. Together they form a unique fingerprint.

  • Cite this

    Nemes, C., Nagy, Z., & Szolgay, P. (2012). Automatic generation of locally controlled arithmetic unit via floorplan based partitioning. In 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 [6331442] (International Workshop on Cellular Nanoscale Networks and their Applications). https://doi.org/10.1109/CNNA.2012.6331442