Analysis of 2D operators on topographic and non-topographic processor architectures

Ákos Zarándy, Csaba Rekeczky, Péter Földesy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

2D operators were categorized based on their implementation methods on different low-power topographic and non-topographic single-chip processor architectures. The implementation methods of the 2D operators in the individual categories are shown, and their processor utilization efficiency is analyzed. The execution times of the basic operators on the different architectures are calculated, the power efficiency figures and the frame-rate versus resolution chart are derived.

Original languageEnglish
Title of host publication2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures
Pages57-62
Number of pages6
DOIs
Publication statusPublished - Sep 23 2008
Event2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures - Santiago de Compostela, Spain
Duration: Jul 14 2008Jul 16 2008

Publication series

NameProceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

Other

Other2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures
CountrySpain
CitySantiago de Compostela
Period7/14/087/16/08

ASJC Scopus subject areas

  • Software

Cite this

Zarándy, Á., Rekeczky, C., & Földesy, P. (2008). Analysis of 2D operators on topographic and non-topographic processor architectures. In 2008 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008, Cellular Nano-scale Architectures (pp. 57-62). [4588650] (Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications). https://doi.org/10.1109/CNNA.2008.4588650