Die attach delamination in power electronic devices is a common failure mode besides bond wire damage. This paper describes the chip and packaging level effects of a newly developed power cycling test on novel mid-power automotive MOSFETs. The introduced method was pilot tested with our new approach, using a recently developed test environment. The idea was to combine the existent guidelines of the most relevant semiconductor characterization and cycling standards while saving time and resources during testing. Thermal transient measurements during the actively mimicked temperature cycling reliability test were evaluated along with K-factor calibration to identify different failure modes. This approach allows distinguishing between electrical and thermal related structural failure modes. The major target was to test the reliability of a new thermal interface material which was used in the MOSFETs under test. We found that the new material was able to withstand the 150 °C temperature amplitude beyond 100,000 cycles without critical failures. The changes of the thermal performance of the complete assembly were tracked from the pre-stress state until a sample reached critical condition.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Safety, Risk, Reliability and Quality
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering