In this paper we address the chip-level thermal simulation problem. Our work is based on some early results treating electro-thermal problems on circuit level. In our approach for the self-consistent electro-thermal simulation we apply the idea of mapping the thermal networks into an electrical equivalent. In this way the entire electro-thermal simulation problem can be treated simultaneously, by usual circuit simulation algorithms. The applied layout extractor has been extended such that the electrical netlist is completed by a thermal subnetwork which is identified by a quick thermal simulation tool. The developed electro-thermal simulation package has been integrated under Cadence DFWII (Opus). Due to its relatively low CPU need this package can be used as a thermal verification tool of layouts of analog circuits.