3D multi-layer vision architecture for surveillance and reconnaissance applications

Peter Földesy, Ricardo Carmona-Galan, Ákos Zarándy, Csaba Rekeczky, Angel Rodríguez-Vázquez, Tamás Roska

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320x240 sensor array layer, closely coupled with a 160x120 mixed-signal processor array layer, a digital frame buffer layer, and an 8x8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS.

Original languageEnglish
Title of host publicationECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
Pages185-188
Number of pages4
DOIs
Publication statusPublished - Dec 10 2009
EventECCTD 2009 - European Conference on Circuit Theory and Design Conference Program - Antalya, Turkey
Duration: Aug 23 2009Aug 27 2009

Publication series

NameECCTD 2009 - European Conference on Circuit Theory and Design Conference Program

Other

OtherECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
CountryTurkey
CityAntalya
Period8/23/098/27/09

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Földesy, P., Carmona-Galan, R., Zarándy, Á., Rekeczky, C., Rodríguez-Vázquez, A., & Roska, T. (2009). 3D multi-layer vision architecture for surveillance and reconnaissance applications. In ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program (pp. 185-188). [5274944] (ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program). https://doi.org/10.1109/ECCTD.2009.5274944