3D integrated scalable focal-plane processor array

Péter Földesy, A. Zarándy, Csaba Rekeczky, T. Roska

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The ASIC implementation of a 64×64 sized mixedsignal Cellular Visual Microprocessor architecture with digital processors is described. Measurement results are shown. The architecture is composed of a regular photosensor readout circuit array, prepared for 3D sensor integration, an array of identical SIMD processing elements, and central program scheduler. The processing architecture supports cluster formation of differently parameterized arrays.

Original languageEnglish
Title of host publicationEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
Pages954-957
Number of pages4
DOIs
Publication statusPublished - 2008
EventEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain
Duration: Aug 26 2007Aug 30 2007

Other

OtherEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
CountrySpain
CitySeville
Period8/26/078/30/07

Fingerprint

Parallel processing systems
Application specific integrated circuits
Processing
Microprocessor chips
Networks (circuits)
Sensors

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Földesy, P., Zarándy, A., Rekeczky, C., & Roska, T. (2008). 3D integrated scalable focal-plane processor array. In European Conference on Circuit Theory and Design 2007, ECCTD 2007 (pp. 954-957). [4529756] https://doi.org/10.1109/ECCTD.2007.4529756

3D integrated scalable focal-plane processor array. / Földesy, Péter; Zarándy, A.; Rekeczky, Csaba; Roska, T.

European Conference on Circuit Theory and Design 2007, ECCTD 2007. 2008. p. 954-957 4529756.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Földesy, P, Zarándy, A, Rekeczky, C & Roska, T 2008, 3D integrated scalable focal-plane processor array. in European Conference on Circuit Theory and Design 2007, ECCTD 2007., 4529756, pp. 954-957, European Conference on Circuit Theory and Design 2007, ECCTD 2007, Seville, Spain, 8/26/07. https://doi.org/10.1109/ECCTD.2007.4529756
Földesy P, Zarándy A, Rekeczky C, Roska T. 3D integrated scalable focal-plane processor array. In European Conference on Circuit Theory and Design 2007, ECCTD 2007. 2008. p. 954-957. 4529756 https://doi.org/10.1109/ECCTD.2007.4529756
Földesy, Péter ; Zarándy, A. ; Rekeczky, Csaba ; Roska, T. / 3D integrated scalable focal-plane processor array. European Conference on Circuit Theory and Design 2007, ECCTD 2007. 2008. pp. 954-957
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