0.5 μm CMOS CNN analog random access memory chip for massive image processing

R. Carmona, S. Espejo, R. Dominguez-Castro, A. Rodriguez-Vazquez, T. Roska, T. Kozek, L. O. Chua

Research output: Contribution to conferencePaper

15 Citations (Scopus)

Abstract

An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor require fast and efficient short-time signal storage in an analog buffer. This can be achieved by an extended sample and hold scheme able to address every sample to specific memory locations. Several arrays of capacitors are multiplexed sharing controlling circuitry and I/O buses. The design has the following key parameters: 637 analog memory cells/mm2 with 0.4% accuracy, 100 ns access time and 170 ms storage time (within 1% error).

Original languageEnglish
Pages271-276
Number of pages6
Publication statusPublished - Jan 1 1998
EventProceedings of the 1998 5th IEEE International Workshop on Cellular Neural Networks and Their Applications, CNNA - London, UK
Duration: Apr 14 1998Apr 17 1998

Other

OtherProceedings of the 1998 5th IEEE International Workshop on Cellular Neural Networks and Their Applications, CNNA
CityLondon, UK
Period4/14/984/17/98

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ASJC Scopus subject areas

  • Software

Cite this

Carmona, R., Espejo, S., Dominguez-Castro, R., Rodriguez-Vazquez, A., Roska, T., Kozek, T., & Chua, L. O. (1998). 0.5 μm CMOS CNN analog random access memory chip for massive image processing. 271-276. Paper presented at Proceedings of the 1998 5th IEEE International Workshop on Cellular Neural Networks and Their Applications, CNNA, London, UK, .