An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor require fast and efficient short-time signal storage in an analog buffer. This can be achieved by an extended sample and hold scheme able to address every sample to specific memory locations. Several arrays of capacitors are multiplexed sharing controlling circuitry and I/O buses. The design has the following key parameters: 637 analog memory cells/mm2 with 0.4% accuracy, 100 ns access time and 170 ms storage time (within 1% error).
|Number of pages||6|
|Publication status||Published - Jan 1 1998|
|Event||Proceedings of the 1998 5th IEEE International Workshop on Cellular Neural Networks and Their Applications, CNNA - London, UK|
Duration: Apr 14 1998 → Apr 17 1998
|Other||Proceedings of the 1998 5th IEEE International Workshop on Cellular Neural Networks and Their Applications, CNNA|
|Period||4/14/98 → 4/17/98|
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